PLL circuits are extensively used in various electronic circuits as the circuits for generating an internal clock signal synchronized with an input reference clock signal. FIG. 7 shows a conventional common PLL circuit using a block diagram. A PLL circuit 30 includes a phase comparator 31, a charge pump 32, a low-pass filter 33, and a voltage-controlled oscillator 34. By feed backing the output of the voltage-controlled oscillator 34 to the phase comparator 31, these are connected to a loop. The phase comparator 31 compares the phase of a reference clock signal RF_CLK with the phase of a feedback clock signal FB_CLK to each other, and generates an UP signal or a DOWN signal, which is a phase difference signal, based on the result of the comparison.
The charge pump 32 accumulates charge in an output node thereof based on the UP signal which is the output of the phase comparator 31, thereby raising its output voltage (output potential). Alternatively, the charge pump 32 discharges charge from the output node thereof based on the DOWN signal to drop its output voltage. The low-pass filter 33 removes high frequency components of the output voltage of the charge pump 32, for supply to the voltage-controlled oscillator 34. The voltage-controlled oscillator 34 generates a clock signal having a frequency dependent on an output voltage VC of the charge pump 33 received through the low-pass filter 33. The voltage-controlled oscillator 34 outputs the clock signal externally, and also supplies the clock signal to the phase comparator 31 as the feedback clock signal FB_CLK.
FIG. 8 shows a circuit example of the charge pump 32. The charge pump 32 includes an nMOS transistor MN4 through which a reference current flows from a current source not shown and current mirror circuits constituted from nMOS transistors MN3 and MN1 and pMOS transistors MP1 and MP3. The nMOS transistors MN3 and MN1 mirror-reflect the reference current that flows through this nMOS transistor MN4. The pMOS transistor MP3 is connected in series with the nMOS transistor MN3. The pMOS transistor MP1 mirror-reflects the current that flows through this pMOS transistor MP3. The pMOS transistor MP2 inputs the UP signal at a gate thereof, and charges the output node of the charge pump 32 by the reference current output from the pMOS transistor MP1 during a period in which the UP signal at a low level continues to be output. The nMOS transistor MN2 inputs the DOWN signal at a gate thereof and discharges charge from the output node of the charge pump by the reference current output from the nMOS transistor MN1 during a period in which the DOWN signal at a high level continues to be output.
In the PLL circuit 30 described above, when the phases of the reference clock signal RF_CLK and the feedback clock signal FB_CLK are locked, the phase comparator 31 outputs the UP signal at the low level and the DOWN signal at the high level for a same period, respectively, balances the amount of charge for charging the output node with the amount of charge extracted from the output node, and thereby maintains the output voltage VC of the charge pump at a constant value.
Depending on the output voltage VC of the charged pump, a mirror ratio between the pMOS transistor MP1 and the nMOS transistor MN1 of the current mirror circuit sometimes becomes out of balance, and the transistors MP1 and MN1 might have different current driving capabilities. In this case, even if the pulse width of the UP signal is the same as the pulse width of the DOWN signal, the amount of charge for charging the output node of the charge pump becomes different from the amount of charge extracted from the output node. As a result, the output voltage VC of the charge pump varies. In order to maintain the output voltage VC to be constant in such a condition, it is necessary to give an offset between the UP signal and the DOWN signal, thereby equating the amounts of charges for charging and extraction. However, the offset given between the UP signal and the DOWN signal makes it presence as the offset of phases of the signals input to the two inputs of the phase comparator for comparison. In other words, the unbalance that occurs in the charge pump makes its presence as the phase offset between the reference clock signal and the feedback clock signal i.e., an output clock signal, as seen from the outside of the PLL circuit, and this is not desirable.
In order to adjust the unbalance described above, various circuit configurations have been proposed up to now. FIG. 9 shows a charge pump that has adopted a typical approach to adjusting the unbalance, shown in Patent Document 1. In this example, a pMOS transistor MP13 and an nMOS transistor MN13 that have the same size as the pMOS transistor MP1 and the nMOS transistor MN1, respectively, are prepared for, and these, the pMOS transistor MP1, and the nMOS transistor MN1 constitute current mirror circuits. The drain of the transistor MP13 and the drain of the transistor MN13 are connected to each other. A potential VCDM at the node connecting the transistors MP13 and MN13 is compared with an output potential VC of the charge pump by an operational amplifier 35, and the output voltage of the operational amplifier 35 is supplied to the gates of a pMOS transistor MP16 and an nMOS transistor MN16 of which their drains are connected to each other.
In a charge pump circuit described in the above Patent Document 1, the transistors MP13, MN13, MP16, and MN16, transistors MP15 and MN15, and the operational amplifier 35 constitute a feedback circuit. The operational amplifier 35 performs control so that the potential VCDM is the same as the potential VC. Further, the transistors MP16 and MP15 and the transistors MN16 and MN15 constitute source follower circuits, respectively.
If a difference between the amounts of charges that flow through the transistor MP13 and the transistor MN13 is produced and the unbalance is caused, the potential VCDM varies. Thus, currents flow from the source follower circuits so that this unbalance is counteracted. The currents that have flown also flow through transistors MP2 and MN2 that constitute the main charge pump, through current mirror circuits constituted from the transistor MP15 and a transistor MP14 and from the transistor MN15 and a transistor MN14, thereby adjusting the output potential VC of the charge pump. With this arrangement, like the unbalance caused between the transistors MP13 and MN13, the unbalance that would be also produced between the transistors MP1 and MN1 that constitute the main charge pump is counteracted.
[Patent Document 1] U.S. Pat. No. 5,508,660